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Integrated Circuit Systems, Inc.
ICS9248-162
Frequency Generator & Integrated Buffers for PENTIUM/ProTM & K6
General Description
The ICS9248-162 is the single chip clock solution for various mobile chipset platforms. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-162 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.
Features
Up to 137MHz frequency support Spread Spectrum for EMI control Serial I2C interface for Power Management, Frequency Select, Spread Spectrum. Provides the following system clocks - 4-CPUs @ 2.5/3.3V, up to 137MHz. (including CPUCLK_F) - 9-SDRAMs @3.3V, up to 137MHz (including SDRAM_F) - 8-PCI @3.3V, CPU/2 or CPU/3 (including 1 free running PCICLK_F) - 1-24/48MHz @3.3V - 1-48MHz @3.3V fixed - 2-REF @3.3V, 14.318MHz. Efficient Power management scheme through PCI and CLK STOP CLOCKS Spread Spectrum .25%, & 0 to -0.5% down spread

Block Diagram
PLL2 48MHz /2 X1 X2 BUFFER IN CPUCLK_F PLL1 Spread Spectrum FS(3:0) SEL24_48#
STOP
Pin Configuration
VDDREF REF0 GNDREF X1 X2 VDDPCI *CPU2.5_3.3#/PCICLK_F *FS3/PCICLK0 GNDPCI *SEL24_48#/PCICLK1 PCICLK2 PCICLK3 PCICLK4 VDDPCI BUFFER IN GNDPCI PCICLK5 PCICLK6 VDDCOR PCI_STOP# *PD# GND48 SDATA SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 REF1/FS2* VDDLCPU CPUCLK_F CPUCLK0 GNDLCPU CPUCLK1 CPUCLK2 CLK_STOP# GNDSDR SDRAM_F SDRAM0 SDRAM1 VDDSDR SDRAM2 SDRAM3 GNDSDR SDRAM4 SDRAM5 VDDSDR SDRAM6 SDRAM7 VDD48 48MHz/FS0* 24_48MHz/FS1*
24_48MHz
2
XTAL OSC
REF(1:0)
3
CPUCLK (2:0)
LATCH
STOP
8
SDRAM (7:0) SDRAM_F
POR
CLK_STOP# PCI_STOP# CPU2.5_3.3# SDATA SCLK PD# Control Logic Config. Reg.
PCI CLOCK DIVDER
STOP
7
PCICLK (6:0) PCICLK_F
Power Groups
VDDLCPU, GNDLCPU = CPUCLK [2:0], CPUCLK_F VDDSDR, GNDSDR = SDRAMCLKS [7:0], SDRAM_F VDDPCI, GNDPCI = PCICLKS [6:0], PCICLK_F VDD48, GND48 = 48MHz, 24MHz VDDREF, GNDREF = REF, X1, X2 VDDCOR = PLL CORE
9248-162 Rev A 8/31/00
48-Pin SSOP and TSSOP
* Internal Pull-up Resistor of 120K to VDD
Pentium is a trademark of Intel Corporation I2C is a trademark of Philips Corporation
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS9248-162
ICS9248-162
Pin Descriptions
PIN NUMBER 1 2 20 3, 9, 16, 33, 40, 44 4 5 6,14 7 8 10 18, 17, 13, 12, 11, 15 19 21 22 28, 29, 31, 32, 34, 35, 37, 38 30, 36 23 24 25 26 27 39 41 42, 43, 45 46 47 48 P I N NA M E VDDREF REF0 PCI_STOP# GND X1 X2 VDDPCI C P U 2 . 5 _ 3 . 3 # 1,2 PCICLK_F FS31,2 PCICLK0 SEL24_48#1,2 PCICLK1 PCICLK (6:2) BUFFER IN VDDCOR PD#1 GND48 SDRAM (7:0) VDDSDR SDATA SCLK 24_48MHz FS11, 2 48MHz FS01, 2 VDD48 SDRAM_F CLK_STOP# CPUCLK [2:0] CPUCLK_F VDDLCPU REF1 FS21, 2 TYPE PWR OUT IN PWR IN OUT PWR IN OUT IN OUT IN OUT OUT IN PWR IN PWR OUT PWR I/O IN OUT IN OUT IN PWR OUT IN OUT OUT PWR OUT IN DESCRIPTION Ref, XTAL power supply, nominal 3.3V 14.318 Mhz reference clock.This REF output is the STRONGER buffer for ISA BUS loads Halts PCICLK clocks at logic 0 level, when input low (In mobile mode, MODE=0) Ground Crystal input, has internal load cap (36pF) and feedback resistor from X2 Crystal output, nominally 14.318MHz. Supply for PCICLK_F and PCICLK , nominal 3.3V Indicates whether VDDLCPU is 2.5 or 3.3V. High=2.5V CPU, LOW=3.3V CPU. Latched Input. Free running PCI clock not affected by PCI_STOP# for power management. Frequency select pin. Latched Input. PCI clock output. Synchronous to CPU clocks with 1-4ns skew (CPU early) Selects either 24 or 48MHz when Low =48 MHz PCI clock output. Synchronous to CPU clocks with 1-4ns skew (CPU early) PCI clock outputs. Synchronous to CPU clocks with 1-4ns skew (CPU early) Input to Fanout Buffers for SDRAM outputs. Power pin for the PLL core. 3.3V Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 4ms. Ground pin for the 24 & 48MHz output buffers & fixed PLL core. SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin (controlled by chipset). Supply for SDRAM and CPU PLL Core, nominal 3.3V. Data pin for I2C circuitry 5V tolerant Clock input of I2C input, 5V tolerant input 24MHz or 48MHz output clock selectable by pin 10 Frequency select pin. Latched Input. 48MHz output clock Frequency select pin. Latched Input Power for 24 & 48MHz output buffers and fixed PLL core. Free running SDRAM clock output. Not affected by CPU_STOP# This asynchronous input halts CPUCLK, & SDRAM clocks at logic "0" level when driven low. CPU clock outputs, powered by VDDLCPU Free running CPU clock. Not affected by the CPU_STOP# Supply for CPU clocks 2.5V 14.318 MHz reference clock. Frequency select pin. Latched Input
Notes: 1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low.
2
ICS9248-162
Functionality
VDD = 3.3V5%, VDDL= 2.5V5% or 3.35%, TA=0 to 70C Crystal (X1, X2) = 14.31818MHz
FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU (MHz) 124.00 120.00 114.99 109.99 105.00 83.31 137.00 75.00 100.00 95.00 97.00 133.33 90.00 96.22 66.82 91.5 PCI (MHz) 41.33 40.00 38.33 36.66 35.00 41.65 34.25 37.50 33.33 31.67 32.33 33.33 30.00 32.07 33.41 30.5
Serial Configuration Command Bitmap
Bit Bit 7
Byte0: Functionality and Frequency Select Register (default = 0)
Description 0 - 0.25% Spread Spectrum Modulation, Center Spread 1 - 0 to -0.5% Down Spread CPUCLK PCICLK Bit [2, 6:4] (MHz) (MHz) 0000 124.00 41.33 0001 120.00 40.00 0010 114.99 38.33 0011 109.99 36.66 0100 105.00 35.00 0101 83.31 41.65 0110 137.00 34.25 0111 75.00 37.50 1000 100.00 33.33 1001 95.00 31.67 1010 97.00 32.33 1011 133.33 33.33 1100 90.00 30.00 1101 96.22 32.07 1110 66.82 33.41 1111 91.5 30.5 0 - Frequency is selected by hardware select, latched inputs 1 - Frequency is selected by Bit (2, 6:4) 0 - Normal 1 - Spread Spectrum Enabled 0 - Running 1- Tristate all outputs PWD 1
Bit [2, 6:4]
Note1
Bit 3 Bit 1 Bit 0
0 1 0
Notes: 1, Default at Power-up will be for latched logic inputs to define frequency. Bit (2, 6:4) are default to 0010. 2, PWD = Power-Up Default 3, When disabling spread spectrum bit7 needs to be set to 0 to maintain nominal frequency.
3
ICS9248-162
Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 46 39 42 43 45 PWD 1 1 1 1 1 1 1 1 Description (Reserved) CPUCLK_F (Act/Inact) (Reserved) (Reserved) SDRAM_F (Act/Inact) CPUCLK2 (Act/Inact) CPUCLK1 (Act/Inact) CPUCLK0 (Act/Inact)
Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 7 18 17 13 12 11 10 8 PWD 1 1 1 1 1 1 1 1 Description PCICLK_F (Act/Inact) PCICLK6 (Act/Inact) PCICLK5 (Act/Inact) PCICLK4 (Act/Inact) PCICLK3 (Act/Inact) PCICLK2 (Act/Inact) PCICLK1 (Act/Inact) PCICLK0 (Act/Inact)
Byte 3: SDRAM Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 28 29 31 32 PWD 1 1 1 1 1 1 1 1 Description (Reserved) (Reserved) (Reserved) (Reserved) SDRAM7 (Active/Inactive) SDRAM6 (Active/Inactive) SDRAM5 (Active/Inactive) SDRAM4 (Active/Inactive)
Notes: 1. Inactive means outputs are held LOW and are disabled from switching. 2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.
4
ICS9248-162
Byte 4: Reserved Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # PWD 1 1 X 1 X 1 X 1 Description (Reserved) (Reserved) (SEL24_48)# (Reserved) Latched FS1# (Reserved) Latched FS3# (Reserved)
Byte 5: Peripheral Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 34 35 37 38 26 25 48 2 PWD 1 1 1 1 1 1 1 1 Description SDRAM3 (Act/Inact) SDRAM2 (Act/Inact) SDRAM1 (Act/Inact) SDRAM0 (Act/Inact) 48MHz (Act/Inact) 24MHz (Act/Inact) REF1 (Act/Inact) REF0 (Act/Inact)
Notes: 1. Inactive means outputs are held LOW and are disabled from switching. 2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.
5
ICS9248-162
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 5.5 V GND 0.5 V to VDD +0.5 V 0C to +70C 115C 65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Input High Voltage VIH Input Low Voltage VIL CL = 0 pF; Select @ 66MHz Operating Supply IDD3.3OP CL = 0 pF; Select @ 100MHz Current CL = 0 pF; Select @ 133MHz IDDPD Powerdown Current CL = 0 pF; Input address VDD or GND Input Frequency Fi VDD = 3.3 V Input Capacitance1 Clk Stabilization1 Skew1
1
MIN 2 VSS-0.3
12 27 1
MAX VDD+0.3 0.8 90 150 120 170 151 180 250 600 14.318 16 36 2.8 5 45 5.5 4
TYP
UNITS V V mA A MHz pF pF ms ns
CIN CINX TSTAB tCPU-PCI1
Logic Inputs X1 & X2 pins From VDD = 3.3 V to 1% target Freq. VT = 1.5 V
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70 C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP 8 CL = 0 pF; Select @ 66.8 MHz IDDL2.5 Operating SupplyCurren 11 CL = 0 pF; Select @ 100 MHz 17 CL = 0 pF; Select @ 133 MHz IDDLPD Powerdown Current CL = 0 pF; Input address VDD or GND <1 1 tCPU-PCI2 VT = 1.5 V; VTL = 1.25 V 1 2.4 Skew
1
MAX 15 18 20 10 4
UNITS mA A ns
Guaranteed by design, not 100% tested in production.
6
ICS9248-162
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20 pF PARAMETER SYMBOL IOH = -20 mA Output High Voltage VOH2A IOL = 12 mA Output Low Voltage VOL2A Output High Current IOH2A VOH = 2.0 V Output Low Current IOL2A VOL = 0.8 V Rise Time Fall Time
1
CONDITIONS
MIN 2.4
22
TYP 2.85 0.31 -45 29 1.5 1.4
MAX 0.4 -27 2 2 55 175 250
UNITS V V mA mA ns ns % ps ps
tr2A tf2A dt2A
1
VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V 45
1 1
Duty Cycle
Skew window Jitter, Cycle-to-cycle1
1
tsk2A tjcyc-cyc2A
80 200
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPU
TA = 0 - 70C; VDDL = 2.5 V +/-5%; CL = 20 pF PARAMETER SYMBOL IOH = -12 mA Output High Voltage VOH2B IOL = 12 mA Output Low Voltage VOL2B VOH = 1.7 V Output High Current IOH2B VOL = 0.7 V Output Low Current IOL2B Rise Time Fall Time
1
CONDITIONS
MIN 2
22
TYP 2.3 0.31 -39 26 1.3 1.4 47.5 47 70 200
MAX 0.4 -21 1.6 1.6 55 52 175 300
UNITS V V mA mA ns ns % ps ps
tr2B tf2B dt2B tsk2B tjcyc-cyc2B
VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V, < 133 MHz VT = 1.25 V, >= 133 MHz VT = 1.25 V VT = 1.25 V 45 42
1
Duty Cycle1 Skew window1 Jitter, Cycle-to-cycle1
1
Guaranteed by design, not 100% tested in production.
7
ICS9248-162
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF PARAMETER SYMBOL CONDITIONS Output High Voltage VOH1 IOH = -18 mA Output Low Voltage VOL1 IOL = 9.4 mA Output High Current IOH1 VOH = 2.0 V Output Low Current IOL1 VOL = 0.8 V Rise Time Fall Time
1
MIN 2.4
38
TYP 3 0.2 -62 43 1.5 1.5
MAX 0.4 -33 2 2 55 500 150 250
UNITS V V mA mA ns ns % ps ps ps
tr1 tf1 dt1
1 1
VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V -250 45
1 1
Duty Cycle
50 180 15 75
Skew window
tsk1 tj1s1 tjabs1
Jitter, One Sigma Jitter, Absolute1
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time
1 1 1 1 1
SYMBOL VOH3 VOL3 IOH3 IOL3 Tr3 Tf3 Dt3 Tsk3 Tsk3
CONDITIONS IOH = -28 mA IOL = 19 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 2.4
32
TYP 3 0.3 -69 42 1 1.3 50 185 4
MAX 0.4 -46 1.3 2 55 250 5
UNITS V V mA mA ns ns % ps ns
Duty Cycle
45
Skew window
Propagation Time (Buffer In to output)
1
Guaranteed by design, not 100% tested in production.
8
ICS9248-162
Electrical Characteristics - 24,48M Hz, REF
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 - 20 pF (unles s otherwis e s tated) PA RA M ETER Output High Voltage Output Low Voltage Output High Current Output Low Current Ris e Time Fall Time
1 1 1 1
SYM BOL VOH5 VOL5 IOH5 IOL5 tr5 tf5 dt5 tj1s5 tjabs5
CONDITIONS IOH = -14 mA IOL = 6 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
M IN 2.4
16
TYP 2.6 0.22 -32 22 2 2
MAX 0.4 -20 4 4 55 250 600
UNITS V V mA mA ns ns % ps ps
Duty Cycle
45 -600
1 150
Jitter, One Sigma Jitter, A bs olute
1
1
Guaranteed by des ign, not 100% tes ted in production.
9
ICS9248-162
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 ICS clock will acknowledge each byte one at a time. Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Stop Bit
ACK Stop Bit ACK Byte 5 ACK Byte 4 ACK Byte 3 ACK Byte 2 ACK Byte 1 ACK Byte 0
ICS (Slave/Receiver)
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK
ACK Byte Count
Notes:
1. 2. 3. 4. 5.
6.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
10
ICS9248-162
CLK_STOP# Timing Diagram
CLK_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation. CLK_STOP# is synchronized by the ICS9248-162. The minimum that the CPU clock is enabled (CLK_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
INTERNAL CPUCLK PCICLK CLK_STOP# PCI_STOP# (High)
SDRAM CPUCLK CPUCLK _F SDRAM_F
Notes: 1. All timing is referenced to the internal CPU clock. 2. CLK_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPU clocks inside the ICS9248-162. 3. SDRAM-F output is controlled by Buffer in signal, not affected by the ICS9248-162 CLK_STOP# signal. SDRAMs are controlled as shown. 4. All other clocks continue to run undisturbed.
11
ICS9248-162
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 4 mS. The power down latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and CLK_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.
PD#
CPUCLK
PCICLK VCO Crystal
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device). 2. As shown, the outputs Stop Low on the next falling edge after PD# goes low. 3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. 4. The shaded sections on the VCO and the Crystal signals indicate an active clock. 5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
12
ICS9248-162
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-162. It is used to turn off the PCICLK clocks for low power operation. PCI_STOP# is synchronized by the ICS9248-162 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP# high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK clock on latency cycles are only three rising PCICLK clocks, off latency is one PCICLK clock.
CPUCLK (Internal)
PCICLK_F (Internal) PCICLK_F (Free-running) CLK_STOP#
PCI_STOP#
PCICLK
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS9248. 3. All other clocks continue to run undisturbed. 4. CLK_STOP# is shown in a high (true) state.
13
ICS9248-162
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) on the ICS9248162 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad 2K W
Via to VDD
8.2K W Clock trace to load Series Term. Res.
Fig. 1
14
ICS9248-162
SYMBOL
In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX 2.413 0.203 0.203 2.794 0.406 0.343 .095 .008 .008 .110 .016 .0135
A A1 b c D E E1 e h L N VARIATIONS N 48
0.127 0.254 SEE VARIATIONS 10.033 7.391 0.381 10.668 7.595 0.635
.005 .010 SEE VARIATIONS .395 .291 .015 .420 .299 .025
0.635 BASIC 0.508 1.016 SEE VARIATIONS 0 8
0.025 BASIC .020 .040 SEE VARIATIONS 0 8
D mm. MIN 15.748 MAX 16.002 MIN .620
D (inch) MAX .630
6/1/00 REV B
JEDEC MO-118 DOC# 10-0034
Ordering Information
ICS9248yF-162-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
15
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS9248-162
SYMBOL
In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX 0.05 0.80 0.17 1.20 0.15 1.05 0.27 .002 .032 .007 .047 .006 .041 .011
A A1 A2 b c D E E1 e L N aaa VARIATIONS N
0.09 0.20 SEE VARIATIONS 8.10 BASIC 6.00 6.20
.0035 .008 SEE VARIATIONS 0.319 .236 .244 0.020 BASIC .018 .30 SEE VARIATIONS 0 8 .004
0.50 BASIC 0.45 0.75 SEE VARIATIONS 0 8 0.10
D mm. MIN 12.40 MAX 12.60 MIN .488
D (inch) MAX .496
7/6/00 Rev B
6.10 mm. Body, 0.50 mm. pitch TSSOP (0.020 mil) (240 mil)
48
MO-153 JEDEC Doc.# 10-0039
Ordering Information
ICS9248yG-162-T
Example:
ICS XXXX y G - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type G=TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
16

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